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TVS Diode Arrays (SPA ? Diodes)
General Purpose ESD Protection - SP723 Series
Package Dimensions — Small Outline Plastic Packages (SOIC)
N
INDEX
AREA
E
H
0.25(0.010) M
B M
Package
Pins
SOIC
8
-B-
JEDEC
MS-012
1
2
3
L
Millimeters
Min Max
Inches
Min
Max
Notes
SEATING PLANE
A
1.35
1.75
0.0532
0.0688
-
-A-
D
A
h x 45 o
A1
B
0.10
0.33
0.25
0.51
0.0040
0.013
0.0098
0.020
-
9
-C-
C
0.19
0.25
0.0075
0.0098
-
e
B
A1
0.10(0.004)
C
D
E
4.80
3.80
5.00
4.00
0.1890
0.1497
0.1968
0.1574
3
4
0.25(0.010) M C A M B S
e
1.27 BSC
0.050 BSC
-
Notes:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
H
h
L
5.80
0.25
0.40
6.20
0.50
1.27
0.2284
0.0099
0.016
0.2440
0.0196
0.050
-
5
6
1. Symbolsare de?nedin the “MOSeries SymbolList”in Section 2.2 of
PublicationNumber95.
NOTES:
3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold
flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Inter-lead flash
and protrusions shall not exceed 0.25mm (0.010 inch) per side.
2. chamfer the body is optional. If is not present, a visual
5. The Dimensioningand tolerancingper ANSI Y14.5M-1982. index feature
3. be located within the not crosshatched area.
must Dimension“D”does includemold?ash, protrusionsor gate burrs.
N
μ
0o
8
8o
0o
8
8o
7
-
inch) per side.
lead ?ash and protrusionsshall not exceed 0.25mm (0.010 inch) per
is the length of terminal for gate to a shall not
6. “L” Mold?ash, protrusion and soldering burrs substrate. exceed 0.15mm(0.006
7. “N” is the number of terminal positions.
4. Terminal numbers ” does not reference only.
8. Dimension“E are shown for includeinterlead?ash or protrusions.Inter-
side.
9. The eadl width “B”, as measured 0.36mm (0.014 inch) or greater above the
seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch).
5. The chamferon the bodyis Converted is not present, not
10. Controlling dimension:MILLIMETER. optional.If it inch dimensions are visualindex
feature exact.
necessarily must be located withinthe crosshatchedarea.
6. “L” is the lengthof terminalfor solderingto a substrate.
Part Numbering System positions.
7. “N”is the numberof terminal
8. Terminal numbersare shownfor reference only.
Product Characteristics
SP 723 ** * *
are (SPA necessarilyexact.
? Diodes) G=Green
9. The lead width“B”, as measured0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
TVS Diode Arrays
10. Controllingdimension:MILLIMETER. Convertedinch dimensions
not
P=Lead Free
Series T= Tape and Reel
Package
AB = 8 Ld SOIC
AP = 8 Ld PDIP
Ordering Information
Lead Plating
Lead Material
Lead Coplanarity
Substitute Material
Body Material
Flammability
Matte Tin
Copper Alloy
0.004 inches (0.102mm)
Silicon
Molded Epoxy
UL 94 V-0
Part Number
SP723APP
SP723ABG
Temp. Range (oC)
-40 to 105
-40 to 105
Package
8 Ld PDIP
8 Ld SOIC
Environmental
Informaton
Lead-free
Green
Marking
SP723AP(P) 1
SP723A(B)G 2
Min. Order
2000
1960
SP723ABTG
-40 to 105
8 Ld SOIC Tape and Reel
Green
SP723A(B)G
2
2500
Notes:
1. SP723AP(P) means device marking either SP723AP or SP723APP.
2. SP723A(B)G means device marking either SP723AG or SP723ABG which are good for types SP723ABG and SP723ABTG.
? 2013 Littelfuse, Inc.
Specifications are subject to change without notice.
Revised: 04/24/13
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